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M27C256B
256 Kbit (32Kb x 8) UV EPROM and OTP EPROM
5V 10% SUPPLY VOLTAGE in READ OPERATION FAST ACCESS TIME: 45ns LOW POWER CONSUMPTION: - Active Current 30mA at 5MHz - Standby Current 100A PROGRAMMING VOLTAGE: 12.75V 0.25V PROGRAMMING TIME: 100s/byte (PRESTO II ALGORITHM) ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code: 8Dh
28
28
1
1
FDIP28W (F)
PDIP28 (B)
DESCRIPTION The M27C256Bis a 256 KbitEPROM offeredin the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems and is organized as 32,768 by 8 bits. The FDIP28W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C256B is offered in PDIP32, PLCC32 and TSOP28 (8 x 13.4 mm) packages.
PLCC32 (C)
TSOP28 (N) 8 x 13.4mn
Figure 1. Logic Diagram
VCC
VPP
15 A0-A14
8 Q0-Q7
Table 1. Signal Names
A0-A14 Q0-Q7 E G VPP VCC VSS Address Inputs Data Outputs Chip Enable Output Enable Program Supply Supply Voltage Ground
E G
M27C256B
VSS
AI00755B
July 1998
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M27C256B
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
AI00756
Q1 Q2 VSS DU Q3 Q4 Q5
AI00757
VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS
1 28 2 27 3 26 4 25 5 24 6 23 7 22 M27C256B 8 21 9 20 10 19 11 18 12 17 13 16 14 15
VCC A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3
A6 A5 A4 A3 A2 A1 A0 NC Q0
A7 A12 VPP DU VCC A14 A13 1 32 A8 A9 A11 NC G A10 E Q7 Q6 9 M27C256B 25 17
Warning: NC = Not Connected, DU = Dont't Use.
Figure 2C. TSOP Pin Connections
G A11 A9 A8 A13 A14 VCC VPP A12 A7 A6 A5 A4 A3
22
21
28 1
M27C256B
15 14
7
8
AI00614B
A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2
DEVICE OPERATION The operating modes of the M27C256B are listed in the Operating Modes. A single power supply is requiredin the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature. Read Mode The M27C256B has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equalto the delay from E to output (tELQV). Data is available at the output after delay of t GLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least t AVQV-tGLQV. Standby Mode The M27C256B has a standby mode which reduces the supplycurrentfrom 30 mA to 100A. The M27C256B is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.
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M27C256B
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO
(2)
Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltages (except A9) Supply Voltage A9 Voltage Program Supply Voltage
(3)
Value -40 to 125 -50 to 125 -65 to 150 -2 to 7 -2 to 7 -2 to 13.5 -2 to 14
Unit C C C V V V V
V CC VA9
(2)
VPP
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is -0.5V with possible undershoot to -2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range.
Table 3. Operating Modes
Mode Read Output Disable Program Verify Program Inhibit Standby Electronic Signature
Note: X = VIH or VIL, VID = 12V 0.5V
E VIL VIL VIL Pulse VIH VIH VIH VIL
G VIL VIH VIH VIL VIH X VIL
A9 X X X X X X VID
VPP VCC VCC VPP VPP VPP VCC VCC
Q0 - Q7 Data Out Hi-Z Data In Data Out Hi-Z Hi-Z Codes
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VIH Q7 0 1 Q6 0 0 Q5 1 0 Q4 0 0 Q3 0 1 Q2 0 1 Q1 0 0 Q0 0 1 Hex Data 20h 8Dh
Two Line Output Control BecauseEPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur.
For the most efficientuse of thesetwo controllines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device.
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M27C256B
Table 5. AC Measurement Conditions
High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V Standard 20ns 0.4V to 2.4V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V
AI01822
1N914
3.3k
Standard 2.4V
OUT CL
0.4V
CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 C, f = 1 MHz )
Symbol CIN C OUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
System Considerations The power switching characteristics of Advance CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of this transient current peaks is dependent on the capacitiveand inductiveloading of the deviceat the output.
The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1F ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7F bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.
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M27C256B
Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70C, -40 to 85C, -40 to 105C or -40 to 125C; VCC = 5V 5% or 5V 10%; VPP = VCC)
Symbol ILI ILO ICC ICC1 ICC2 IPP VIL VIH
(2)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS
Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIL, IOUT = 0mA, f = 5MHz E = VIH E > VCC - 0.2V VPP = VCC
Min
Max 10 10 30 1 100 100
Unit A A mA mA A A V V V V V
-0.3 2 IOL = 2.1mA IOH = -1mA IOH = -100A 3.6 VCC - 0.7
0.8 VCC + 1 0.4
VOL VOH
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70C, -40 to 85C, -40 to 105C or -40 to 125C; VCC = 5V 5% or 5V 10%; VPP = VCC)
M27C256B Symbol Alt Parameter Test Condition -45
(3)
-60
-70
-80
Unit
Min Max Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 45 45 25 25 25 0 0 0
Max Min Max Min Max 60 60 30 30 30 0 0 0 70 70 35 30 30 0 0 0 80 80 40 30 30 ns ns ns ns ns ns
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. In case of 45ns speed see High Speed AC measurement conditions.
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M27C256B
Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70C, -40 to 85C, -40 to 105C or -40 to 125C; VCC = 5V 5% or 5V 10%; VPP = VCC)
M27C256B Symbol Alt Parameter Test Condition -90 Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ
(2)
-10 Min Max 100 100 50 0 0 0 30 30 0 0 0
-12 Min Max 120 120 60 40 40
-15/-20/-25 Min Max 150 150 65 0 0 0 50 50
Unit
Max 90 90 40
tACC tCE tOE tDF tDF tOH
Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0
ns ns ns ns ns ns
30 30
tAXQX
Notes: 1. VCC must be applied simultaneously with or before V PP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A14
VALID tAVQV tAXQX
VALID
E tGLQV G tELQV Q0-Q7 tGHQZ Hi-Z tEHQZ
AI00758B
Programming When delivered (and after each erasure for UV EPROM), all bits of the M27C256B are in the "1" state. Data is introduced by selectively programming "0"s into the desired bit locations. Although only "0"s will be programmed, both "1"s and "0"s can be present in the data word. The only way to
changea '0' to a '1' is by die expositionto ultraviolet light (UV EPROM). The M27C256B is in the programming mode when VPP input is at 12.75V, G is at VIH and E is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25 V 0.25 V.
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M27C256B
Table 9. Programming Mode DC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol ILI ICC IPP VIL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = -1mA 3.6 11.5 12.5 E = VIL -0.3 2 Test Condition VIL VIN VIH Min Max 10 50 50 0.8 VCC + 0.5 0.4 Unit A mA mA V V V V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol tAVEL tQVEL tVPHEL tVCHEL tELEH tEHQX tQXGL tGLQV tGHQZ tGHAX Alt tAS tDS tVPS tVCS tPW tDH tOES tOE tDFP tAH Parameter Address Valid to Chip Enable Low Input Valid to Chip Enable Low VPP High to Chip Enable Low VCC High to Chip Enable Low Chip Enable Program Pulse Width Chip Enable High to Input Transition Input Transition to Output Enable Low Output Enable Low to Output Valid Output Enable High to Output Hi-Z Output Enable High to Address Transition 0 0 Test Condition Min 2 2 2 2 95 2 2 100 130 105 Max Unit s s s s s s s ns ns ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
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M27C256B
Figure 6. Programming and Verify Modes AC Waveforms
A0-A14 tAVEL Q0-Q7 DATA IN tQVEL VPP tVPHEL VCC tVCHEL E tELEH G
VALID
DATA OUT tEHQX
tGLQV
tGHQZ
tGHAX
tQXGL
PROGRAM
VERIFY
AI00759
Figure 7. Programming Flowchart
VCC = 6.25V, VPP = 12.75V
n =0
E = 100s Pulse NO ++n = 25 YES NO VERIFY YES Last Addr NO ++ Addr
FAIL
YES CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V
AI00760B
PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows to program the whole array with a guaranteedmargin, in a typical time of 3.5 seconds. Programming with PRESTO II involves the application of a sequence of 100s programpulses to each byte untila correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides necessary margin to each programmed cell. Program Inhibit Programming of multiple M27C256Bs in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27C256B may be common. A TTL low level pulse applied to a M27C256B's E input, with VPP at 12.75 V, will program that M27C256B. A high level E input inhibits the other M27C256Bs from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with G at VIL, E at VIH, VPP at 12.75V and VCC at 6.25V.
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M27C256B
On-Board Programming The M27C256B can be directly programmed in the application circuit. See the relevant Application Note AN620. Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its correspondingprogramming algorithm. The ES mode is functional in the 25C 5C ambient temperature range that is required when programming the M27C256B. To activate the ES mode, the programming equipmentmust force 11.5Vto 12.5V on address line A9 of the M27C256B, with VCC = VPP = 5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0=VIL) represents the manufacturer code and byte 1 (A0=VIH) the device identifier code. For the STMicroelectronics M27C256B, these two identifier bytes are given in Table 4 and can be read-out on outputs Q0 to Q7. ERASURE OPERATION (applies for UV EPROM) The erasure characteristics of the M27C256B is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 A. It shouldbe notedthat sunlight and some type of fluorescent lamps have wavelengthsin the 3000-4000A range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27C256B in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27C256B is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C256B window to prevent unintentional erasure. The recommended erasure procedurefor the M27C256B is exposure to short wave ultraviolet light which has wavelength 2537A. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 W/cm2 power rating. The M27C256B should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure.
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M27C256B
ORDERING INFORMATION SCHEME Example: M27C256B -70 X C 1 TR
Speed -45 (1) -60 -70 -80 -90 -10 -12 -15 -20 -25 45 ns 60 ns 70 ns 80 ns 90 ns 100 ns 120 ns 150 ns 200 ns 250 ns
VCC Tolerance X blank 5% 10% F B C N
Package FDIP28W PDIP28 PLCC32 TSOP28 8 x 13.4mm
Temperature Range 1 6 7 3 0 to 70 C -40 to 85 C -40 to 105 C -40 to 125 C TR X
Option Additional Burn-in Tape & Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further informationon any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M27C256B
FDIP28W - 28 pin Ceramic Frit-seal DIP, with window
Symb Typ A A1 A2 B B1 C D E E1 e1 e3 eA L S N 7.11 2.54 33.02 15.40 13.05 - - 16.17 3.18 1.52 - 4 28 0.50 3.90 0.40 1.17 0.22 mm Min Max 5.71 1.78 5.08 0.55 1.42 0.31 38.10 15.80 13.36 - - 18.32 4.10 2.49 - 15 0.280 0.100 1.300 0.606 0.514 - - 0.637 0.125 0.060 - 4 28 0.020 0.154 0.016 0.046 0.009 Typ inches Min Max 0.225 0.070 0.200 0.022 0.056 0.012 1.500 0.622 0.526 - - 0.721 0.161 0.098 - 15
A2
A3 A1 B1 B D2 D S
N 1
A L eA eB C
e
E1
E
FDIPW-a
Drawing is not to scale.
11/15
M27C256B
PDIP28 - 28 pin Plastic DIP, 600 mils width
Symb Typ A A1 A2 B B1 C D D2 E E1 e1 eA eB L S N 2.54 14.99 33.02 15.24 1.52 mm Min - 0.38 3.56 0.38 - 0.20 36.83 - - 13.59 - - 15.24 3.18 1.78 0 28 17.78 3.43 2.08 10 Max 5.08 - 4.06 0.51 - 0.30 37.34 - - 13.84 0.100 0.590 1.300 0.600 0.060 Typ inches Min - 0.015 0.140 0.015 - 0.008 1.450 - - 0.535 - - 0.600 0.125 0.070 0 28 Max 0.200 - 0.160 0.020 - 0.012 1.470 - - 0.545 - - 0.700 0.135 0.082 10
A2 A1 B1 B D2 D S
N
A L eA eB C
e1
E1
1
E
PDIP
Drawing is not to scale.
12/15
M27C256B
PLCC32 - 32 lead Plastic Leaded Chip Carrier - rectangular
Symb Typ A A1 A2 B B1 D D1 D2 E E1 E2 e F R N Nd Ne CP 0.89 1.27 mm Min 2.54 1.52 - 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 - 0.00 - 32 7 9 0.10 Max 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 - 0.25 - 0.035 0.050 Typ inches Min 0.100 0.060 - 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 - 0.000 - 32 7 9 0.004 Max 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 - 0.010 -
D D1
1N
A1 A2
B1
Ne
E1 E
F 0.51 (.020)
D2/E2 B
e
1.14 (.045)
Nd
A R CP
PLCC
Drawing is not to scale.
13/15
M27C256B
TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm
Symb Typ A A1 A2 B C D D1 E e L N CP 0.55 0.10 13.10 11.70 7.90 0.30 0 28 0.10 0.95 mm Min 1.00 Max 1.25 0.20 1.05 0.30 0.21 13.70 11.90 8.25 0.70 5 0.022 0.004 0.516 0.461 0.311 0.012 0 28 0.004 0.037 Typ inches Min 0.039 Max 0.049 0.008 0.041 0.012 0.008 0.539 0.469 0.325 0.028 5
A2
22 21
e
28 1
E B
7 8
D1 D
A CP
DIE
C
TSOP-c
Drawing is not to scale.
A1
L
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M27C256B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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